The present disclosure relates to semiconductor device fabrication, and more specifically, to methods of mitigating contact punch through in a semiconductor-on-insulator (SOI) substrate. Semiconductor-on-insulator technology (SOI) typically refers to the use of a layered semiconductor-insulator-semiconductor substrate in place of a more conventional semiconductor substrate (bulk substrate) in semiconductor manufacturing, especially microelectronics. SOI-based devices differ from conventional silicon-built devices in that the semiconductor junction is above an electrical insulator, typically silicon dioxide or (less commonly) sapphire. The choice of insulator depends largely on intended application, with sapphire being used for radiation-sensitive applications and silicon oxide preferred for improved performance and diminished short channel effects in microelectronics devices. The precise thickness of the insulating layer and topmost semiconductor-on-insulator (SOI) layer also vary widely with the intended application. SOI substrates are commonly used to form a large variety of devices such as: static random access memory (SRAM), clock synchronized RAM (CSRAM), logic devices, etc.
During formation of semiconductor devices, electrical contacts are formed through dielectric layers to electrically interconnect desired components with other components, e.g., source, drain or gates of a transistor. Each component is positioned within a selected layer within the semiconductor device that is covered by a dielectric. Typically, the contacts are formed by patterning a mask over the dielectric layer and etching to form an opening in the dielectric to the desired component therebelow. The opening is then filled with a liner and a conductor to form the contact. One challenge relative to forming contacts using SOI substrates is ensuring the contact opening does not extend into the layer below, which is referred to as “punch through.” Punch through leads to the contact being in the wrong location and possibly making the device non-functional. Consequently, punch through can cause problems with yield during fabrication and/or performance degradation of the final device. The challenge of controlling punch through is magnified with smaller semiconductor devices, especially with current technology that is now creating wires smaller than 32 nanometers (nm). One approach to address punch through with SOI substrates is to control the etch selectivity of whatever etching technique is employed. This approach however is not always effective because, for example, it is difficult to effectively detect end points of the etching for the small contacts.
One type of punch through is referred to as “edge punch through” and refers to over-etching into a divot or recess next to a shallow trench isolation (STI) at the boundary of different regions of the substrate, e.g., between an active region and another region. STI is a form of isolation in which a trench is etched into the substrate and filled with an insulating material such as oxide, to isolate one region of the substrate from an adjacent region of the substrate. One or more transistors of a given polarity may be disposed within an area isolated by STI. Edge punch through can cause direct shorts to the underlying substrate.